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  ht47r20a-1/ht47c20-1 r-f type 8-bit mcu rev. 1.80 1 june 23, 2008 features  operating voltage: 2.2v~5.5v  eight bidirectional i/o lines  four input lines  one interrupt input  one 16-bit programmable timer/event counter with pfd (programmable frequency divider) function  on-chip crystal and rc oscillator for system clock  one 32.768khz crystal oscillator for real time clock or system clock  watchdog timer  2k  16 program memory  64  8 data memory ram  one real time clock (rtc)  one 8-bit prescaler for rtc  one low voltage detector  one low voltage reset circuit  one buzzer output  halt function and wake-up feature reduce power consumption  lcd bias c type or r type  one lcd driver with 20  2, 20  3or19  4 segments  one ir carrier output  two channels rc type a/d converter  four-level subroutine nesting  bit manipulation instruction  16-bit table read instruction  up to 1  s instruction cycle with 4mhz system clock  all instructions in one or two machine cycles  63 powerful instructions  64-pin lqfp package general description the ht47r20a-1/ht47c20-1 are 8-bit, high perfor - mance, risc architecture microcontroller devices spe - cifically designed for applications that interface directly to analog signals, such as those from sensors. the mask version ht47c20-1 is fully pin and functionally compatible with the otp version ht47r20a-1 device. the advantages of low power consumption, i/o flexibil - ity, programmable frequency divider, timer functions, oscillator options, 2-channel rc type a/d converter, lcd driver, halt and wake-up functions, enhance the versatility of these devices to suit a wide range of resis - tor to frequency application possibilities such as sensor signal processing, remote metering, industrial control, consumer products, subsystem controllers, etc. technical document  tools information  faqs  application note  ha0029e using the time base function in the ht47r20a-1  ha0030e using the rtc in the ht47r20a-1  ha0034e using the buzzer function in the ht47r20a-1  ha0036e using the pfd function in the ht47r20a-1  ha0045e distinguishing between the different devices in the ht47 mcu series
block diagram ht47r20a-1/ht47c20-1 rev. 1.80 2 june 23, 2008        
                                            
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pin assignment pad description pad name i/o option function pa0/bz pa1/bz pa2/ir pa3/pfd pa4~pa7 i/o wake-up pull-high or none cmos or nmos bidirectional 8-bit input/output port. the low nibble of the pa can be configured as cmos output or nmos output with or without pull-high resistors (determined by pull-high option). nmos output can be configured as schmitt trigger input with or without pull-high resistors. each bit of nmos output can be configured as wake up input by options. of the eight bits, pa0~pa1 can be set as i/o pins or buzzer outputs by options. pa2 can be set as an i/o pin or an ir carrier output also by options. pa3 can be set as an i/o pin or a pfd output also by options. pb0/int pb1 pb2/tmr pb3 i  4-bit schmitt trigger input port. the pb is configured with pull-high resistors. of the four bits, pb0 can be set as an input pin or an external interrupt input pin (int ) by software application. while pb2 can be set as an input pin or a timer/event counter input pin also by software application. in0 cs0 rs0 crt0 rt0 i o o o o  oscillation input pin of channel 0 reference capacitor connection pin of channel 0 reference resistor connection pin of channel 0 resistor/capacitor sensor connection pin for measurement of channel 0 resistor sensor connection pin for measurement of channel 0 in1 cs1 rs1 rt1 i o o o  oscillation input pin of channel 1 reference capacitor connection pin of channel 1 reference resistor connection pin of channel 1 resistor sensor connection pin for measurement of channel 1 com0~com2 com3/seg19 o 1 / 2, 1 / 3or 1 / 4 duty seg19/com3 can be set as segment or common output driver for lcd panel by options. com0~com2 are outputs for lcd panel plate. seg0~seg18 o  lcd driver outputs for lcd panel segments v1, v2, c1, c2  voltage pump vlcd i  lcd power supply osc2 osc1 o i crystal or rc osc1 and osc2 are connected to an rc network or a crystal (by options) for the in - ternal system clock. ht47r20a-1/ht47c20-1 rev. 1.80 3 june 23, 2008                          
                                                                                                  
     
              
                                                                                       
               
    
                    
         

 
pad name i/o option function osc4 osc3 o i rtc or system clock real time clock oscillators osc3 and osc4 are connected to a 32768hz crystal oscillator for timing pur - poses or to a system clock source (depending on the options). res i  schmitt trigger reset input. active low. vss  negative power supply, ground vdd  positive power supply test1~3 i  test mode input pin it disconnects in normal operation. absolute maximum ratings supply voltage ...........................v ss  0.3v to v ss +6.0v storage temperature ............................  50  cto125  c input voltage..............................v ss  0.3v to v dd +0.3v operating temperature...........................  40  cto85  c note: these are stress ratings only. stresses exceeding the range specified under  absolute maximum ratings  may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics ta=25  c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage  f sys =4mhz 2.2  5.5 v f sys =8mhz 3.3  5.5 v i dd1 operating current (crystal osc) 3v no load, f sys =4mhz  0.7 1.5 ma 5v  1.7 3 ma i dd2 operating current (rc osc) 3v no load, f sys =4mhz  0.7 1.5 ma 5v  1.7 3 ma i dd3 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz  48ma i dd4 operating current (f sys =32768hz) 3v no load  0.25 0.5 ma 5v  0.8 1.5 ma i stb1 standby current (*f s =t1) 3v no load, system halt, lcd off at halt  1  a 5v  2  a i stb2 standby current (*f s =32.768khz osc) 3v no load, system halt, lcd on at halt, c type  2.5 5  a 5v  10 20  a i stb3 standby current (*f s =wdt rc osc) 3v no load, system halt lcd on at halt, c type  25  a 5v  610  a i stb4 standby current (*f s =32.768khz osc) 3v no load, system halt, lcd on at halt, r type, 1 / 2 bias  17 30  a 5v  34 60  a i stb5 standby current (*f s =32.768khz osc) 3v no load, system halt, lcd on at halt, r type, 1 / 3 bias  13 25  a 5v  28 50  a ht47r20a-1/ht47c20-1 rev. 1.80 4 june 23, 2008
symbol parameter test conditions min. typ. max. unit v dd conditions i stb6 standby current (*f s =wdt rc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 2 bias  14 25  a 5v  26 50  a i stb7 standby current (*f s =wdt rc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 3 bias  10 20  a 5v  19 40  a v il1 input low voltage for i/o ports, tmr and int  0  0.3v dd v v ih1 input high voltage for i/o ports, tmr and int 3v  0.7v dd  v dd v 5v 0.7v dd  v dd v v il2 input low voltage (res )  0  0.4v dd v v ih2 input high voltage (res )  0.9v dd  v dd v i ol1 i/o port sink current 3v v ol =0.1v dd 612  ma 5v 10 25  ma i oh1 i/o port source current 3v v oh =0.9v dd  2 -4  ma 5v  5  8  ma i ol2 lcd common and segment current 3v v ol =0.1v dd 210 420  a 5v 350 700  a i oh2 lcd common and segment current 3v v oh =0.9v dd  80  160  a 5v  180  360  a i ol3 rc oscillation output sink current 3v v ol =0.3v 510  ma i oh3 rc oscillation output source current 3v v oh =2.7v  5  10  ma r ph pull-high resistance of i/o ports and int0 , int1 3v  20 60 100 k  5v 10 30 50 k  v lvr low voltage reset   2.5 3.2 3.6 v v lvd low voltage detector voltage  3.0 3.3 3.6 v note:  *  t sys = 1/f sys  **  for power on protection ht47r20a-1/ht47c20-1 rev. 1.80 5 june 23, 2008
a.c. characteristics ta=25  c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc)  2.2v~5.5v 400  4000 khz  3.3v~5.5v 400  8000 khz f sys2 system clock (rc osc)  2.2v~5.5v 400  4000 khz  3.3v~5.5v 400  8000 khz f sys3 system clock (32768hz crystal osc)   32768  hz f rtcosc rtc frequency   32768  hz f timer timer i/p frequency  2.2v~5.5v 0  4000 khz  3.3v~5.5v 0  8000 khz t wdtosc watchdog oscillator period 3v  45 90 180  s 5v  35 65 130  s t res external reset low pulse width  1  s t sst system start-up timer period  wake-up from halt  1024  t sys t int interrupt pulse width  1  s ht47r20a-1/ht47c20-1 rev. 1.80 6 june 23, 2008
ht47r20a-1/ht47c20-1 rev. 1.80 7 june 23, 2008 functional description execution flow the system clock for the ht47r20a-1/ht47c20-1 is derived from either a crystal or an rc oscillator. the system clock is internally divided into four non-overlap - ping clocks. one instruction cycle consists of four sys - tem clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute in one cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter  pc the 11-bit program counter (pc) controls the sequence in which the instructions stored in the program memory are executed and its contents specify a maximum of 2048 addresses. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by 1. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupt, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 locations. when a control transfer takes place, an additional dummy cycle is required.
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ht47r20a-1/ht47c20-1 rev. 1.80 8 june 23, 2008 program memory  eprom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 2048  16 bits, addressed by the program counter and ta - ble pointer. certain locations in the program memory are reserved for special usage  location 000h this area is reserved for the initialization program. af - ter chip reset, the program always begins execution at location 000h.  location 004h this area is reserved for the external interrupt service program. if the int interrupt is enabled and the stack is not full, the program begins execution at location 004h.  location 008h this area is reserved for the time base interrupt ser - vice program. if time base interrupt results from a time base overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at loca - tion 008h.  location 00ch this area is reserved for the real time clock interrupt service program. if a real time clock interrupt results from a real time clock overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00ch.  location 010h this area is reserved for the timer/event counter inter- rupt service program. if a timer interrupt results from a timer/event counter a or b overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010h.  table location any location in the rom space can be used as look up tables. the instructions tabrdc [m] (the current page, one page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the tblh. the ta - ble higher-order byte register (tblh) is read only. the table pointer (tblp) is a read/write register (07h), which indicates the table location. before accessing the table, the location must be placed in tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in other words, using the table read instruction in the main routine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt is supposed to be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related instructions need two cycles to complete the operation. these ar- eas may function as normal program memory de- pending upon the requirements. stack register  stack this is a special part of the memory which is used to save the contents of the program counter (pc) only. the stack is organized into four levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledg - ment, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the program counter is restored to its previous value instruction(s) table location *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *10~*0: table location bits @7~@0: table pointer bits p10 p8: current program counter bits    8   8   6 8   4    )       +  @     ) #    =     + )      #  )   a            % ! : ) a    & , >  # )   a +  ) ;  9 : ) 7   < 3 1 1 8   b )  )     ) (  )  )  ) 3    8
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ht47r20a-1/ht47c20-1 rev. 1.80 9 june 23, 2008 from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a  call  is sub - sequently executed, stack overflow occurs and the first entry will be lost (only the most recent four return ad - dresses are stored). data memory  ram the data memory is designed with 85  8 bits. the data memory and is divided into two functional groups: spe - cial function registers and general purpose data mem - ory (64  8). most are read/write, but some are read only. the special function registers include the indirect ad - dressing register 0 (00h), the memory pointer register 0 (mp0; 01h), the indirect addressing register 1 (02h), the memory pointer register 1 (mp1;03h), the bank pointer (bp;04h), the accumulator (acc;05h), the program counter lower-order byte register (pcl;06h), the table pointer (tblp;07h), the table higher-order byte register (tblh;08h), the real time clock control register (rtcc;09h), the status register (status;0ah), the in- terrupt control register 0 (intc0;0bh), the i/o registers (pa;12h, pb;14h), the interrupt control register 1 (intc1;1eh), the timer/event counter a higher order byte register (tmrah;20h), the timer/event counter a lower or- der byte register (tmral;21h), the timer/event counter control register (tmrc;22h), the timer/event counter b higher order byte register (tmrbh;23h), the timer/event counter b lower order byte register (tmrbl;24h), and the rc oscillator type a/d converter control register (adcr; 25h). the remaining space before the 40h are reserved for future expanded usage and reading these location will return the result 00h. the general purpose data memory, addressed from 40h to 7fh, is used for data and control information under instruction command. all data memory areas can handle arithmetic, logic, in - crement, decrement and rotate operations. except for some dedicated bits, each bit in the data memory can be set and reset by the set [m].i and clr [m].i instruction, respectively. they are also indirectly accessible through memory pointer registers (mp0;01h, mp1;03h).      + )   #       )    % ; : )  %    < 3 1 8   8 
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ht47r20a-1/ht47c20-1 rev. 1.80 10 june 23, 2008 indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] access data memory pointed to by mp0 (01h) and mp1 (03h) respectively. reading location 00h or 02h indirectly will return the result 00h. writing indirectly results in no operation. the function of data movement between two indirect ad - dressing registers are not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers which can be used to access the data memory by com - bining corresponding indirect addressing registers. only mp0 can be applied to data memory, while mp1 can be applied to data memory and lcd display mem - ory. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and is capable of carrying out immediate data operations. the data movement between two data memory loca - tions must pass through the accumulator. arithmetic and logic unit  alu this circuit performs 8-bit arithmetic and logic operation. the alu provides the following functions:  arithmetic operations (add, adc, sub, sbc, daa)  logic operations (and, or, xor, cpl)  rotation (rl, rr, rlc, rrc)  increment and decrement (inc, dec)  branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but can change the status register. status register  status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf) and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flags. in addition it should be noted that operations related to the status register may give different results from those intended. the to and pdf flags can only be changed by the watchdog timer overflow, system power-up, clearing the watchdog timer and executing the halt instruction. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status are important and if the subroutine can cor - rupt the status register, precautions must be taken to save it properly. interrupts the ht47r20a-1/ht47c20-1 provides an external in- terrupt, an internal timer/event counter interrupt, an in- ternal time base interrupt, and an internal real time clock interrupt. the interrupt control register 0 (intc0;0bh) and interrupt control register 1 (intc1;1eh) both con- tain the interrupt control bits to set the enable or disable and interrupt request flags. bit no. label function 0c c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1ac ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is 0; otherwise z is cleared. 3ov ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared when either a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7  unused bit, read as  0  status (0ah) register
ht47r20a-1/ht47c20-1 rev. 1.80 11 june 23, 2008 once an interrupt subroutine is serviced, all other inter - rupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may happen during this inter- val, but only the interrupt request flag is recorded. if a certain interrupt needs servicing within the service rou- tine, the emi bit and the corresponding bit of intc0 or intc1 may be set allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupt have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then by branching to subroutines at specified location(s) in the program memory. only the program counter is pushed onto the stack. if the contents of the register and status register (status) is altered by the interrupt service program which corrupts the desired control sequence, the contents must be saved first. external interrupt is triggered by a high to low transition of int and the related interrupt request flag (eif; bit 4 of intc0) will be set. when the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (tf; bit 4 of intc1), caused by a timer a or timer b over - flow. when the interrupt is enabled, and the stack is not full and the tf bit is set, a subroutine call to location 10h will occur. the related interrupt request flag (tf) will be reset and the emi bit cleared to disable further inter - rupts. the time base interrupt is initialized by setting the time base interrupt request flag (tbf; bit 5 of intc0), caused by a regular time base signal. when the interrupt is en- abled, and the stack is not full and the tbf bit is set, a subroutine call to location 08h will occur. the related in- terrupt request flag (tbf) will be reset and the emi bit cleared to disable further interrupts. the real time clock interrupt is initialized by setting the real time clock interrupt request flag (rtf; bit 6 of intc0), caused by a regular real time clock signal. when the interrupt is enabled, and the stack is not full and the rtf bit is set, a subroutine call to location 0ch will occur. the related interrupt request flag (rtf) will be reset and the emi bit cleared to disable further inter - rupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are held until the reti instruc - tion is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti instruction may be invoked. reti will set the emi bit to enable an in - terrupt service, but ret does not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. bit no. label function 0 emi control the master (global) interrupt (1= enabled; 0= disabled) 1 eei control the external interrupt (1= enabled; 0= disabled) 2 etbi control the time base interrupt (1= enabled; 0= disabled) 3 erti control the real time clock interrupt (1= enabled; 0= disabled) 4 eif external interrupt request flag (1= active; 0= inactive) 5 tbf time base request flag (1= active; 0= inactive) 6 rtf real time clock request flag (1= active; 0= inactive) 7  unused bit, read as  0  intc0 (0bh) register bit no. label function 0 eti control the timer/event counter interrupt (1= enabled; 0=disabled) 1~3  unused bit, read as  0  4 tf internal timer/event counter request flag (1= active; 0= inactive) 5~7  unused bit, read as  0  intc1 (1eh) register
ht47r20a-1/ht47c20-1 rev. 1.80 12 june 23, 2008 interrupt source priority vector external interrupt 1 04h time base interrupt 2 08h real time clock interrupt 3 0ch timer/event counter interrupt 4 10h the external interrupt request flag (eif), real time clock interrupt request flag (rtf), time base interrupt request flag (tbf), enable external interrupt bit (eei), enable real time clock interrupt bit (erti), enable time base in - terrupt bit (etbi), and enable master interrupt bit (emi) constitute an interrupt control register 0 (intc0) which is located at 0bh in the data memory. the timer/event counter interrupt request flag (tf), enable timer/event counter interrupt bit (eti) on the other hand, constitute an interrupt control register 1 (intc1) which is located at 1eh in the data memory. emi, eei, eti, etbi, and erti are used to control the enabling/disabling of inter - rupts. these bits prevent the requested interrupt being serviced. once the interrupt request flags (rtf, tbf, tf, eif) are set, they remain in the intc1 or intc0 re - spectively until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the  call subroutine  within the interrupt subroutine. be- cause interrupts often occur in an unpredictable manner or need to be serviced immediately in some applica- tions, if only one stack is left, and enabling the interrupt is not well controlled, once the  call subroutine  oper- ates in the interrupt subroutine will damage the original control sequence. oscillator configuration the ht47r20a-1/ht47c20-1 provides three oscillator circuits for system clocks, i.e., rc oscillator, crystal os - cillator and 32768hz crystal oscillator, determined by options. no matter what type of oscillator is selected, the signal is used for the system clock. the halt mode stops the system oscillator (rc and crystal oscillator only) and ignores external signal to conserve power. the 32768hz crystal oscillator (system oscillator) still runs at halt mode. if the 32768hz crystal oscillator is selected as the system oscillator, the system oscillator is not stopped; but the instruction execution is stopped. since the (used as system oscillator or rtc oscillator) is also designed for timing purposes, the internal timing (rtc, time base, wdt) operation still runs even if the system enters the halt mode. of the three oscillators, if the rc oscillator is used, an external resistor between osc1 and is required, and the range of the resistance should be from 24k  to 1m  . the system clock, divided by 4, is available on osc2 with pull-high resistor, which can be used to syn - chronize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of the oscillation may vary with vdd, temperature, and the chip itself due to process variations. it is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. on the other hand, if the crystal oscillator is selected, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. a resonator may be connected between osc1 and osc2 to replace the crystal and to get a frequency reference, but two ex - ternal capacitors in osc1 and osc2 are required. there is another oscillator circuit designed for the real time clock. in this case, only the 32.768khz crystal oscil - lator can be applied. the crystal should be connected between osc3 and osc4. the rtc oscillator circuit can be controlled to oscillate quickly by setting the qosc bit (bit 4 of rtcc). it is rec- ommended to turn on the quick oscillating function upon power on, and then turn it off after 2 seconds. the oscillator is a free running on-chip rc oscillator, and no external components are required. although the system enters the power down mode, the system clock stops, and the wdt oscillator still works with a period of approximately 90  s@3v. the wdt oscillator can be disabled by options to conserve power. watchdog timer  wdt the clock source of the wdt (f s ) is implemented by a dedicated rc oscillator (wdt oscillator) or a instruction clock (system clock divided by 4) or a real time clock os - cillator (rtc oscillator), decided by options. the timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable re - sults. the watchdog timer can be disabled by options. if the watchdog timer is disabled, all the executions re - lated to the wdt result in no operation.  %    + )     + +       b ) (  -   )    ) #   )        !     (  -   0  3 : 6 8 @ )  %    +  
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ht47r20a-1/ht47c20-1 rev. 1.80 13 june 23, 2008 if the clock source of wdt chooses the internal wdt oscillator, the time-out period may vary with tempera - ture, vdd, and process variations. on the other hand, if the clock source selects the instruction clock and the  halt  instruction is executed, wdt may stop count - ing and lose its protecting purpose, and the logic can only be restarted by external logic. when the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom- mended, since the halt can cease the system clock. the wdt overflow under normal operation will initialize  chip reset  and set the status bit to. whereas in the halt mode, the overflow will initialize a  warm reset  only the program counter and sp are reset to 0. to clear the contents of wdt, three methods are adopted, external reset (a low level to res ), software instruction, or a halt instruction. the software instructions are of two types which include clr wdt and the other set  clr wdt1 and clr wdt2. of these two types of instruction, only one can be active depending on the rom code option   clr wdt times selection option  .ifthe  clr wdt  is selected (i.e., clr wdt times equal one), any execution of the clr wdt instruction will clear the wdt. in case  clr wdt1  and  clr wdt2  are chosen (i.e. clr wdt times equal two), these two instructions must be exe - cuted to clear the wdt; otherwise, the wdt may reset the chip because of time-out. the wdt time-out period ranges from 2 15 /f s ~2 16 /f s .be - cause the  clr wdt  or  clr wdt1  and  clr wdt2  instruction only clear the last two-stage of the wdt. multi-function timer the ht47r20a-1/ht47c20-1 provides a multi-function timer for wdt, time base and real time clock but with dif - ferent time-out periods. the multi-function timer con - sists of a 8-stage divider and an 7-bit prescaler, with the clock source coming from wdt osc or rtc osc or the instruction clock (i.e., system clock divided by 4). the multi-function timer also provides a selectable fre - quency signal (ranges from f s /2 2 to f s /2 8 ) for lcd driver circuits, and a selectable frequency signal (ranges from f s /2 2 to f s /2 9 ) for buzzer output by options. it is recom - mended to select a 4khz signal for lcd driver circuits for proper display. time base the time base offers a periodic time-out period to gener- ate a regular internal interrupt. its time-out period ranges from f s /2 12 to f s /2 15 selected by options. if time base time-out occurs, the related interrupt request flag (tbf; bit 5 of intc0) is set. but if the interrupt is en- abled, and the stack is not full, a subroutine call to loca - tion 08h occurs. when the halt instruction is executed, the time base still works (if wdt clock source comes from wdt rc osc or rtc osc) and can wake up from halt mode. if the tbf is set  1  before entering the halt mode, the wake up function will be disabled. real time clock  rtc the real time clock (rtc) is operated in the same man - ner as the time base that is used to supply a regular inter - nal interrupt. its time-out period ranges from f s /2 8 to f s /2 15 by software programming. writing data to rt2, rt1 and rt0 (bits 2, 1, 0 of rtcc;09h) yields various  %     )  +  ,    4         +  / 
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ht47r20a-1/ht47c20-1 rev. 1.80 14 june 23, 2008 time-out periods. if the rtc time-out occurs, the related interrupt request flag (rtf; bit 6 of intc0) is set. but if the interrupt is enabled, and the stack is not full, a subrou - tine call to location 0ch occurs. the real time clock time-out signal can also be applied to be a clock source of timer/event counter, so as to get a longer time-out period. rt2 rt1 rt0 clock divided factor 000 2 8 * 001 2 9 * 010 2 10 * 011 2 11 * 100 2 12 101 2 13 110 2 14 111 2 15 note:  *  not recommended to be used power down operation  halt the halt mode is initialized by the halt instruction and results in the following.  the system oscillator will turn off but the wdt oscilla - tor or rtc oscillator keeps running (if the wdt oscil - lator or the real time clock is selected).  the contents of the on-chip ram and registers remain unchanged.  the wdt will be cleared and recounted again (if the wdt clock comes from the wdt oscillator or the real time clock oscillator).  all i/o ports maintain their original status.  the pdf flag is set and the to flag is cleared.  lcd driver is still running by rom code option (if the wdt osc or rtc osc is selected). the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a overflow. an external reset causes a device initialization and the wdt overflow performs a  warm reset  . examining the to and pdf flags, the rea - son for chip reset can be determined. the pdf flag is cleared when the system power-up or executing the clr wdt instruction and is set when the halt instruc - tion is executed. the to flag is set if a wdt time-out oc - curs, it causes a wake-up that only resets the program counter and sp, the others maintain their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by rom code option. awakening from an i/o port stimulus, the program will resume execution of the next instruction. if awakening from an interrupt, two se - quences may happen. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the pro - gram will resume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. if an interrupt request flag is set to  1  before entering the halt mode the wake-up function of the related in - terrupt will be disabled. once a wake-up event occurs, it takes 1024 (system clock period) to resume normal operation. in other words, a dummy period will be inserted after the wake-up. if the wake-up results from an interrupt ac - knowledgment, the actual interrupt subroutine execu - tion is delayed by one more cycle. if the wake-up results in the next instruction execution, this will execute imme - diately after a dummy period has finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset  there are three ways in which a reset may occur.  res reset during normal operation  res reset during halt  wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm reset that just resets the program counter and sp leaving the other circuits in their original state. some registers re- main unchanged during any other reset conditions. most registers are reset to the  initial condition  when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different  chip resets  . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note:  u  means  unchanged  .    "   !   ,  !  ,   d !  1 e  d  !  1 e reset circuit note:  *  make the length of the wiring, which is con - nected to the res pin as short as possible, to avoid noise interference.
ht47r20a-1/ht47c20-1 rev. 1.80 15 june 23, 2008 to guarantee that the system oscillator has started and stabilized, the sst (system start-up timer) provides an extra delay. there is an extra delay of 1024 system clock pulses when the system awakes from the halt state or when the system powers up. the functional unit chip reset status are shown below. program counter 000h interrupt disabled prescaler, divider cleared wdt, rtc, time base clear. after master reset, begin counting timer/event counter off input/output ports input mode sp points to the top of the stack the states of the registers are summarized in the following table: register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt) tmrah xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmral xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- tmrbh xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrbl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 1xxx --00 1xxx --00 1xxx --00 1xxx --00 uuuu --uu program counter 000h 000h 000h 000h 000h* mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u rtcc --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu note:  *  refers to warm reset  u  means unchanged  x  means unknown / 
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ht47r20a-1/ht47c20-1 rev. 1.80 16 june 23, 2008 timer/event counter one 16-bit timer/event counter with pfd output or two channels of rc type a/d converter is implemented in the ht47r20a-1/ht47c20-1. the adc/tm bit (bit 1 of adcr register) decides whether timer a and timer b is composed of one 16-bit timer/event counter or timer a and timer b composed of two channels rc type a/d converter. the tmral, tmrah, tmrbl, tmrbh compose one 16-bit timer/event counter, when adc/tm bit is  0  . the tmrbl and tmrbh are timer/event counter preload registers for lower-order byte and higher-order byte re - spectively. using the internal clock, there are three reference time base. the timer/event counter internal clock source may come from the system clock or system clock/4 or rtc time-out signal to generator an accurate time base. using external clock input allows the user to count exter - nal events, count external rc type a/d clock, measure time intervals or pulse widths, or generate an accurate time base. there are six registers related to the timer/event counter operating mode. tmrah ([20h]), tmral ([21h]), tmrc ([22h]), tmrbh ([23h]), tmrbl ([24h]) and adcr ([25h]). writing tmrbl only writes the data into a low byte buffer, and writing tmrbh will write the data and the contents of the low byte buffer into the time/event counter preload register (16-bit) simulta - neously. the timer/event counter preload register is changed by writing tmrbh operations and writing tmrbl will keep the timer/event counter preload regis - ter unchanged. reading tmrah will also latch the tmral into the low byte buffer to avoid the false timing problem. reading tmral returns the contents of the low byte buffer. in other words, the low byte of the timer/event counter can not be read directly. it must read the tmrah first to make the low byte contents of the timer/event counter be latched into the buffer. if the timer/event counter is on, the tmrah, tmral, tmrbh and tmrbl cannot be read or written. to avoid conflicting between timer a and timer b, the tmrah, tmral, tmrbh and tmrbl registers should be accessed with  mov  instruction under timer off condition. the tmrc is the timer/event counter control register, which defines the timer/event counter options. the timer/event counter control register defines the op - erating mode, counting enable or disable and active edge. writing to timer b makes the starting value be placed in the timer/event counter preload register, while reading timer a yields the contents of the timer/event counter. timer b is timer/event counter preload register.
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   timer/event counter bit no. label function 0~2  unused bit, read as  0  3te defines the tmr active edge of timer/event counter (0=active on low to high; 1=active on high to low) 4 ton enable or disable timer counting (0=disable; 1=enable) 5 6 7 tm0 tm1 tm2 defines the operating mode (tm2, tm1, tm0) 000=timer mode (system clock) 001=timer mode (system clock/4) 010=timer mode (rtc output) 011=a/d clock mode (rc oscillation decided by adcr register) 100=event counter mode (external clock) 101=pulse width measurement mode (system clock/4) 110=unused 111=unused tmrc (22h) register
ht47r20a-1/ht47c20-1 rev. 1.80 17 june 23, 2008 the tm0, tm1 and tm2 bits define the operation mode. the event count mode is used to count external events, which means that the clock source comes from an exter - nal (tmr) pin. the a/d clock mode is used to count ex - ternal a/d clock, the rc oscillation mode is decided by adcr register. the timer mode functions as a normal timer with the clock source coming from the internal se - lected clock source. finally, the pulse width measure - ment mode can be used to count the high or low level duration of the external signal (tmr). the counting is based on the instruction clock. in the event count, a/d clock or internal timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter (tmrah and tmral) to ffffh. once overflow occurs, the counter is reloaded from the timer/event counter preload register (tmrbh and tmrbl) and generates the corresponding interrupt request flag (tf; bit 4 of intc1) at the same time. in the pulse width measurement mode with the ton and te bits are equal to 1, once the tmr has received a transient from low to high (or high to low if the te bit is 0) it will start counting until the tmr returns to the original level and resets the ton. the measured result will re - main in the timer/event counter even if the activated transient occurs again. in other words, only one cycle measurement can be done. until setting the ton, the cycle measurement will function again as long as it re- ceives further transient pulse. note that in this operation mode, the timer/event counter starts counting not ac- cording to the logic level but according to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues interrupt request just like the other three modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmrc) should be set to 1. in the pulse width measurement mode, the ton will be automatically cleared after the measurement cycle is completed. but in the other three modes, the ton can only be reset by instructions. the overflow of the timer/event counter is one of the wake-up sources and can also be applied to a pfd (programmable frequency divider) output at pa3 by options. no matter what the operation mode is, writ - inga0toetican disable the corresponding interrupt service. when the pfd function is selected, executing  clr pa.3  instruction to enable pfd output and exe - cuting  set pa.3  instruction to disable pfd output and pa.3 output low level. in the case of timer/event counter off condi tion, writing data to the timer/event counter preload register also re - loads that data to the timer/event counter. but if the timer/event counter turns on, data written to the timer/event counter preload register is kept only in the timer/event counter preload register. the timer/event counter will still operate until overflow occurs. when the timer/event counter (reading tmrah) is read, the clock will be blocked to avoid errors. as this may result in a counting error, this must be taken into consideration by the programmer. it is strongly recommended to load first the desired value for tmrbl, tmrbh, tmral, and tmrah regis- ters, before turning on the related timer/event counter for proper operation. because the initial value of tmrbl, tmrbh, tmral and tmrah are unknown. if the timer/event counter is on, the tmrah, tmral, tmrbh and tmrbl cannot be read or written. only when the timer/event counter is off and when the in- struction  mov  is used could those four registers be read or written. example for timer/event counter mode (disable interrupt): clr tmrc clr adcr.1 ; set timer mode clr intc1.4 ; clear timer/event counter interrupt request flag mov a, low (65536-1000) ; give timer initial value mov tmrbl, a ; count 1000 time and then overflow mov a, high (65536-1000) mov tmrbh, a mov a, 00110000b ; timer clock source=t1 and timer on mov tmrc, a p10: clr wdt snz intcl.4 ; polling timer/event counter interrupt request flag p10 clr intcl.4 ; clear timer/event counter interrupt request flag ; program continue
ht47r20a-1/ht47c20-1 rev. 1.80 18 june 23, 2008 a/d converter two channels of rc type a/d converter are imple - mented in the ht47r20a-1/ht47c20-1. the a/d con - verter contains two 16-bit programmable count-up counter and the timer a clock source may come from the system clock, instruction clock or rtc output. the timer b clock source may come from the external rc os - cillator. the tmral, tmrah, tmrbl, tmrbh is com - posed of the a/d converter when adc/tm bit (bit 1 of adrc register) is  1  . the a/d converter timer b clock source may come from channel 0 (in0 external clock input mode, rs0~cs0 os - cillation, rt0~cs0 oscillation, crt0~cs0 oscillation (crt0 is a resistor), or rs0~crt0 oscillation (crt0 is a capacitor) or channel 1 (rs1~cs1 oscillation, rt1~cs1 oscillation or in1 external clock input). the timer a clock source is from the system clock, instruction clock or rtc prescaler clock output decided by tmrc register. there are six registers related to the a/d converter, i.e., tmrah, tmral, tmrc, tmrbh, tmrbl and adcr. the internal timer clock is input to tmrah and tmral, the a/d clock is input to tmrbh and tmrbl. the ovb/ova bit (bit 0 of adcr register) decides whether timer a overflows or timer b overflows, then the tf bit is set and timer interrupt occurs. when the a/d converter mode timer a or timer b overflows, the ton bit is reset and stop counting. writing tmrah/tmrbh makes the starting value be placed in the timer a/timer b and read- ing tmrah/tmrbh gets the contents of the timer a/timer b. writing tmral/tmrbl only writes the data into a low byte buffer, and writing tmrah/tmrbh will write the data and the contents of the low byte buffer into the timer a/timer b (16-bit) simultaneously. the timer a/timer b is changed by writing tmrah/tmrbh opera - tions and writing tmral/tmrbl will keep timer a/timer b unchanged. reading /tmrbh will also latch the tmral/tmrbl into the low byte buffer to avoid the false timing problem. reading tmral/tmrbl returns the contents of the low byte buffer. in other word, the low byte of timer a/timer b can not be read directly. it must read the tmrah/tmrbh first to make the low byte contents of timer a/timer b be latched into the buffer. if the a/d converter timer a and timer b are count - ing, the tmrah, tmral, tmrbh and tmrbl can - not be read or written. to avoid conflicting between timer a and timer b, the tmrah, tmral, tmrbh and tmrbl registers should be accessed with  mov  instruction under timer a and timer b off con - dition. the bit4~bit7 of adcr decides which resistor and ca - pacitor compose an oscillation circuit and input to tmrbh and tmrbl. the tm0, tm1 and tm2 bits of tmrc define the clock source of timer a. it is recommended that the clock source of timer a use the system clock, instruction clock or rtc prescaler clock. the ton bit (bit 4 of tmrc) is set  1  the timer a and timer b will start counting until timer a or timer b over- flows, the timer/event counter generates the interrupt request flag (tf; bit 4 of intc1) and the timer a and timer b stop counting and reset the ton bit to  0  at the same time. if the ton bit is  1  , the tmrah, tmral, tmrbh and tmrbl cannot be read or written. only when the timer/event counter is off and when the instruc- tion  mov  is used could those four registers be read or written. bit no. label function 0 ovb/ova in the rc type a/d converter mode, this bit is used to define the timer/event counter interrupt which comes from timer a overflow or timer b overflow. (0= timer a overflow; 1= timer b overflow) in the timer/event counter mode, this bit is void. 1 adc/tm defines 16 timer/event counters or rc type a/d converter is enabled. (0= timer/event counter enable; 1= a/d converter is enabled) 2~3  unused bit, read as  0  . 4 5 6 7 m0 m1 m2 m3 defines the a/d converter operating mode (m3, m2, m1, m0) 0000= in0 external clock input mode 0001= rs0~cs0 oscillation (reference resistor and reference capacitor) 0010= rt0~cs0 oscillation (resistor sensor and reference capacitor) 0011= crt0~cs0 oscillation (resistor sensor and reference capacitor) 0100= rs0~crt0 oscillation (reference resistor and sensor capacitor) 0101= rs1~cs1 oscillation (reference resistor and reference capacitor) 0110= rt1~cs1 oscillation (resistor sensor and reference capacitor) 0111= in1 external clock input mode 1xxx= unused mode adcr (25h) register
ht47r20a-1/ht47c20-1 rev. 1.80 19 june 23, 2008 example for rc type ad converter mode (timer a overflow): clr tmrc clr adcr.1 ; set timer mode clr intc1.4 ; clear timer/event counter interrupt request flag mov a, low (65536-1000) ; give timer a initial value mov tmrbl, a ; count 1000 time and then overflow mov a, high (65536-1000) mov tmrbh, a mov a, 00010010b ; rs0~cs0; set rc type adc mode; set timer a overflow mov adcr,a mov a, 00h ; give timer b initial value mov tmrbl, a mov a, 00h mov tmrbh, a mov a, 00110000b ; timer a clock source=t1 and timer on mov tmrc, a p10: clr wdt snz intcl.4 ; polling timer/event counter interrupt request flag jmp p10 clr intcl.4 ; clear timer/event counter interrupt request flag ; program continue example for rc type ad converter mode (timer b overflow): clr tmrc clr adcr.1 ; set timer mode clr intc1.4 ; clear timer/event counter interrupt request flag mov a, 00h ; give timer a initial value mov tmrbl, a mov a, 00h mov tmrbh, a mov a, 00010011b ; rs0~cs0; set rc type adc mode; set timer b overflow adcr, a mov a, low (65536-1000) ; give timer b initial value mov tmrbl, a ; count 1000 time and then overflow mov a, high (65536-1000) mov tmrbh, a mov a, 00110000b ; timer a clock source=t1 and timer on mov tmrc, a p10: clr wdt snz intcl.4 ; polling timer/event counter interrupt request flag jmp p10 clr intcl.4 ; clear timer/event counter interrupt request flag ; program continue
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  !   ! !       !    0   !   0         !       ! ! ! !  !   ! !   ! !    !  !  !  !   ! ! !       9     !      :    !       3  !   !      6   !        5      ! !    !       !     ! !       !    !  ! ! ! ! !      ! 0      ! ! !  rc type a/d converter input/output ports there are 8-bit bidirectional input/output port and 4-bit input port in the ht47r20a-1/ht47c20-1, labeled pa and pb which are mapped to the data memory of [12h] and [14h] respectively. the high nibble of the pa is nmos output and input with pull-high resisters. the low nibble of the pa can be used for input/output or output operation by selecting nmos or cmos output by op - tions. each bit on the pa can be configured as a wake-up input, and the low nibble of the pa with or with - out pull-high resistor by options. pb can only be used for input operation, and each bit is with pull high resistor. both are for the input operation, these ports are non-latched, that is, the inputs should be ready at the t2 rising edge of the instruction  mov a, [m]  (m=12h or 14h). for pa output operation, all data are latched and remain unchanged until the output latch is rewritten. when the structures of pa are open drain nmos type, it should be noted that, before reading data from the pads, a  1  should be written to the related bits to disable the nmos device. that is done first before executing the in - struction  mov a, 0ffh  and  mov [12h], a  to disable related nmos de vice, and then  mov a, [12h]  to get stable data. after chip reset, these input lines remain at a high level or are left floating (by rom code option). some instructions first input data and then follow the output operations. for example,  set [m].i  ,  clr [m].i  ,  cpl [m]  ,  cpla [m]  read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. each bit of the pa output latches can not use these instruction, which may change the input lines to output lines (when input line is at low level).
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ht47r20a-1/ht47c20-1 rev. 1.80 22 june 23, 2008 lcd display memory the ht47r20a-1/ht47c20-1 provides an area of em - bedded data memory for lcd display. the lcd display memory is designed into 20  3 bits. if the lcd selected 19  4 segments output, the 53h of the lcd display memory can not be accessed. this area is located from 40h to 53h of the ram at bank 1. bank pointer (bp; lo - cated at 04h of the data memory) is the switch between the general data memory and the lcd display memory. when the bp is set  1  any data written into 40h~53h will effect the lcd display (indirect addressing mode us - ing mp1). when the bp is cleared  0  , any data written into 40h~53h means to access the general purpose data memory. the lcd display memory can be read and written only by indirect addressing mode using mp1. when data is written into the display data area, it is automatically read by the lcd driver which then gener - ates the corresponding lcd driving signals. to turn the display on or off, a  1  or a  0  is written to the corre - sponding bit of the display memory, respectively. the figure illustrates the mapping between the display mem - ory and lcd pattern for the ht47r20a-1/ht47c20-1. lcd driver output the output number of the ht47r20a-1/ht47c20-1 lcd driver can be 20  2, 20  3or19  4 by options (i.e., 1 / 2 duty, 1 / 3 duty or 1 / 4 duty). the bias type of the lcd driver can be  c  type or  r  type. a capacitor mounted between c1 and c2 pins is needed. the bias voltage of the lcd driver can be 1 / 2 bias or 1 / 3 bias by options. if 1 / 2 bias is selected, a capacitor mounted between v2 pin and the ground is required. if 1 / 3 bias is selected, two capacitors are needed for v1 and v2 pins. refer to the application diagram. if the  r  bias type is selected, no external capacitor is required.     h )    ! h )                          ! "    #      $     "  $      h    ! h     ) " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) $ + + ) ) &   )   4  )   #    )     )    ! )                " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) " &   ) !   ) ) " &   ) "   ) " &   !   ) ) " &   ) "   )      b ) c  c )     ) )  '  )     )     + h )  ( )  '  ) !   )    % ) &   )   )     d &   )        ) )      h ! h )  )      )   )   +  '    )   + % ) &   )        )  ) )     )     )   ) +  '    )   + % ) &   )        )  ) )    ! )     )   ) +  '      + % ) &   )        )  ) )     )     )   ) +  '    &   )        )      h ! )      )   ) +  '    ) &   )        )  ) )     h )  )      )   ) +  '    ) &   )        )     ! h )  )      )   ) +  '    ) &   )        )  )     h ! h )  )      )   ) +  '    ) $ + + ) &   )   4  )   #    lcd driver output (1 / 3 duty, 1 / 2 bias, r/c type)  8     !  0     
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ht47r20a-1/ht47c20-1 rev. 1.80 23 june 23, 2008     )    ! )     )    0 ) &   )        )      )     ) +  '    " $ ) "  "  "   "   "   "   "   " $ ) "  "  " $ ) "  "  " $ ) "  "  " $ ) "  "    b ) !  )    % h ) !  0 ) a    h )  )  % #  b ) c " $ c ) 0   ) " &   h ) c "  c ) " &   h ) c "  c ) !   ) " &   !  )    % h ) !  0 ) a    h )  )  % #  b ) c " $ c ) " &   h ) c "  c )   0 ) " &   h ) c "  c ) !  0 ) " &   lcd driver output low voltage reset/detector functions there is a low voltage detector (lvd) and a low voltage reset circuit (lvr) implemented in the microcontrollers. these two functions can be enabled/disabled by rom code options. the lvd can be enabled/disabled by rom code options. once the rom code options of lvd is enabled, the user can use the rtcc.3 to enable or disable (1/0) the lvd circuit and read the lvd detector status (0/1) from rtcc.5; otherwise, the lvd function is disabled. the lvr has the same effect or function with the exter - nal res signal which performs chip reset. during halt state, lvr is disabled.  !   " ! " &   "   !   " ! "  !  0 ) a    !   ) a    "   " &   "   v1, v2, vlcd application diagram (c type)
ht47r20a-1/ht47c20-1 rev. 1.80 24 june 23, 2008 the definitions of rtcc register are listed in the following table. bit no. label read/write reset function 0~2 rt0~rt2 r/w 1 8 to 1 multiplexer control inputs to select the real clock prescaler output 3 lvdc* r/w 0 lvd enable/disable (1/0) 4 qosc r/w 0 32768hz osc quick start-up oscillating 0/1: quickly/slowly start 5 lvdo r/w 0 lvd detection output (1/0) 1: low voltage detected 6~7  unused bit, read as  0  note:  *  once the function is enabled the reference generator should be enabled; otherwise the reference genera - tor is controlled by lvr rom code option. rtcc (09h) register buzzer ht47r20a-1/ht47c20-1 provides a pair of buzzer out - put bz and bz , which share pins with pa0 and pa1 re - spectively, as determined by options. its output frequency can also be selected by options. when the buzzer function is selected, setting pa.0 and pa.1  0  simultaneously will enable the buzzer output and setting pa.0  1  will disable the buzzer output and setting pa.0  0  and pa.1  1  will only enable the bz output and disable the bz output. pa1 pa0 function 0( clr pa.1) 0 ( clr pa.0) pa0=bz, pa1=bz 1 (set pa.1) 0 ( clr pa.0) pa0=bz, pa1=0 x 1 (set pa.0) pa0=0, pa1=0 buzzer enable ir carrier ht47r20a-1/ht47c20-1 provides carrier driving capa - bility that allows for easy interfacing to an infrared diode, which share pin with pa2, as determined by options. when the carrier option is selected, setting pa2  0  (  clr pa.2  ) will enable the carrier output and setting pa2  1  (  set pa.2  ) will disable the carrier output and the pa2 output is at low level. the ir carrier frequency is system clock divided by 12 and it is 1 / 4 duty. pa2 function 0( clr pa.2) pa2=ir carrier output 1 (set pa.2) pa2=0 programmable frequency divider  pfd the pfd output shares pin with pa3, as determined by options. when the pfd option is selected, setting pa3  0  (  clr pa.3  ) will enable the pfd output and setting pa3  1  (  set pa.3  ) will disable the pfd output and pa3 output at low level. pfd output frequency = 1 2  1 timer overflow period pa3 function 0 (clr pa.3) pa3=pfd output 1 (set pa.3) pa3=0
ht47r20a-1/ht47c20-1 rev. 1.80 25 june 23, 2008 option the following shows many kinds of options in the ht47r20a-1/ht47c20-1. all these options should be defined in or - der to ensure proper system functioning. no. option 1 osc type selection. this option is to decide if an rc, a crystal oscillator or rtc oscillator is chosen as system clock. 2 clock source selection of wdt, rtc and time base. there are three types of selection: system clock/4 or rtc osc or wdt osc. 3 wdt enable or disable selection. wdt can be enabled or disabled. 4 clr wdt times selection. this option defines how to clear the wdt by instruction. one time? means that the  clr wdt  can clear the wdt.  two times  means that only if both of the  clr wdt1  and  clr wdt2  have been executed, then wdt can be cleared. 5 time base time-out period selection. the time base time-out period ranges from f s /2 12 to f s /2 15 .  f s  means the clock source of wdt. 6 buzzer output frequency selection. there are eight types frequency signals for buzzer output: f s /2 2 ~f s / 2 9 .  f s  means the clock source of wdt. 7 wake-up selection. this option defines the wake-up function activity. external i/o pins (pa only) all have the capability to wake-up the chip from a halt mode by a following edge. 8 pull high selection. this option is to decide whether the pull high resistance is viable or not on the low nibble of the pa. 9 pa cmos or nmos selection. the structure of the low nibble of the pa can be selected to be cmos or nmos. when the cmos is selected, the related pins only can be used for output operations. when the nmos is selected, the related pins can be used for input or output operations. 10 i/o pins share with other function selection. pa0/bz, pa1/bz : pa0 and pa1 can be set as i/o pins or buzzer outputs. pa2/ir: pa2 can be set as i/o pins or ir carrier output. pa3/pfd: pa3 can be set as i/o pins or pfd output. 11 lcd common selection. there are three types of selection: 2 common (1 / 2 duty) or 3 common (1 / 3 duty) or 4 common (1 / 4 duty). if the 4 common is selected, the segment output pin  seg32  will be set as a common output. 12 lcd driver clock selection. there are seven types of frequency signals for the lcd driver circuits: f s /2 2 ~f s /2 8 .  f s  means the clock source of wdt. 13 lcd on or lcd off at the halt mode selection. the lcd can be enable or disable at the halt mode. 14 lvd enable or disable 15 lvr enable or disable
application circuits note: the resistance and capacitance for reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res to high.  *  make the length of the wiring, which is connected to the res pin as short as possible, to avoid noise interference. the following table shows the c1, c2 and r1 value according different crystal values. (for reference only) crystal or resonator c1, c2 r1 4mhz crystal 0pf 10k  4mhz resonator (3 pin) 0pf 12k  4mhz resonator (2 pin) 10pf 12k  3.58mhz crystal 0pf 10k  3.58mhz resonator (2 pin) 25pf 10k  2mhz crystal & resonator (2 pin) 25pf 10k  1mhz crystal 35pf 27k  480khz resonator 300pf 9.1k  455khz resonator 300pf 10k  429khz resonator 300pf 10k  the function of the resistor r1 is to ensure that the oscillator will switch off should low voltage condi - tions occur. such a low voltage, as mentioned here, is one which is less than the lowest value of the mcu operating voltage. note however that if the lvr is enabled then r1 can be removed. ht47r20a-1/ht47c20-1 rev. 1.80 26 june 23, 2008  $  2  $ 3    2   0     2    0     2    ! 6  !   " ! "  &    $  & &   )  7  )   # # + % " &    d !  1  d !  1  d !  1          
 
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ht47r20a-1/ht47c20-1 rev. 1.80 27 june 23, 2008 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5  s and branch or call instructions would be im - plemented within 1  s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be  clr pcl  or  mov pcl, a  . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht47r20a-1/ht47c20-1 rev. 1.80 28 june 23, 2008 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the  set [m].i  or  clr [m].i  instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the  halt  in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address
ht47r20a-1/ht47c20-1 rev. 1.80 29 june 23, 2008 mnemonic description cycles flag affected rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the  clr wdt1  and  clr wdt2  instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both  clr wdt1  and  clr wdt2  instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc
acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m]
acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc
acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc
acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m]
acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc
acc  and  [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc
acc  and  x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m]
acc  and  [m] affected flag(s) z ht47r20a-1/ht47c20-1 rev. 1.80 30 june 23, 2008
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack
program counter + 1 program counter
addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m]
00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i
0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to
0 pdf
0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to
0 pdf
0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to
0 pdf
0 affected flag(s) to, pdf ht47r20a-1/ht47c20-1 rev. 1.80 31 june 23, 2008
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m]
[m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc
[m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m]
acc + 00h or [m]
acc + 06h or [m]
acc + 60h or [m]
acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m]
[m]  1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc
[m]  1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to
0 pdf
1 affected flag(s) to, pdf ht47r20a-1/ht47c20-1 rev. 1.80 32 june 23, 2008
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m]
[m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc
[m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter
addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc
[m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc
x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m]
acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc
acc  or  [m] affected flag(s) z ht47r20a-1/ht47c20-1 rev. 1.80 33 june 23, 2008
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc
acc  or  x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m]
acc  or  [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter
stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter
stack acc
x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter
stack emi
1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1)
[m].i; (i = 0~6) [m].0
[m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1)
[m].i; (i = 0~6) acc.0
[m].7 affected flag(s) none ht47r20a-1/ht47c20-1 rev. 1.80 34 june 23, 2008
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1)
[m].i; (i = 0~6) [m].0
c c
[m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1)
[m].i; (i = 0~6) acc.0
c c
[m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i
[m].(i+1); (i = 0~6) [m].7
[m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i
[m].(i+1); (i = 0~6) acc.7
[m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i
[m].(i+1); (i = 0~6) [m].7
c c
[m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i
[m].(i+1); (i = 0~6) acc.7
c c
[m].0 affected flag(s) c ht47r20a-1/ht47c20-1 rev. 1.80 35 june 23, 2008
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc
acc  [m]  c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m]
acc  [m]  c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m]
[m]  1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc
[m]  1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m]
ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i
1 affected flag(s) none ht47r20a-1/ht47c20-1 rev. 1.80 36 june 23, 2008
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m]
[m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc
[m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc
acc  [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m]
acc  [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc
acc  x affected flag(s) ov, z, ac, c ht47r20a-1/ht47c20-1 rev. 1.80 37 june 23, 2008
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0
[m].7 ~ [m].4 acc.7 ~ acc.4
[m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc
[m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m]
program code (low byte) tblh
program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m]
program code (low byte) tblh
program code (high byte) affected flag(s) none ht47r20a-1/ht47c20-1 rev. 1.80 38 june 23, 2008
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc
acc  xor  [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m]
acc  xor  [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc
acc  xor  x affected flag(s) z ht47r20a-1/ht47c20-1 rev. 1.80 39 june 23, 2008
package information 64-pin lqfp (7mm  7mm) outline dimensions symbol dimensions in mm min. nom. max. a 8.9  9.1 b 6.9  7.1 c 8.9  9.1 d 6.9  7.1 e  0.4  f 0.13  0.23 g 1.35  1.45 h  1.6 i 0.05  0.15 j 0.45  0.75 k 0.09  0.20  0  7  ht47r20a-1/ht47c20-1 rev. 1.80 40 june 23, 2008 6 5 0 0 0  : ! ! : ! 3 $     1  8  j . 
ht47r20a-1/ht47c20-1 rev. 1.80 41 june 23, 2008 copyright  2008 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek  s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) g room, 3 floor, no.1 building, no.2016 yi-shan road, minhang district, shanghai, china 201103 tel: 86-21-5422-4590 fax: 86-21-5422-4705 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, gaoxin m 2nd, middle zone of high-tech industrial park, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com


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